Chip sequences used in telecommunications applications requiring a set of N symbols or chip sequences, typically being binary K-tuples, which could be used for example as spreading codes or modulation codes, are often required for use in combination with data streams to generate for example spread spectrum or modulated data streams. This is particularly true for a wireless system such as CDMA (Code Division Multiple Access) or UMTS (Universal Mobile Telecommunications System) in which chip sequences form the basis. Similarly, a system will also generally require the set of chip sequences for the inverse operation of extracting from, for example, the spread spectrum or modulated data streams, the original data stream. The specific characteristics of any set of chip sequences are determined by the use to which the set is put, which may include, but is not limited to, such properties as orthogonality, normality, and completeness. The particular desired characteristics often determine the class or type of chip sequence required. Some common examples of chip sequences are Walsh sequences, Gold codes, and orthogonal Gold codes. The use of a particular type of chip sequence in a telecommunications system often employs either an algorithm to generate the chip sequences or a memory store from which the chip sequences may be retrieved as they are required and used in the system. To maintain all of the desired properties of each chip sequence and the set of chip sequences as a whole, it is important that the algorithm or memory store reliably reproduce the desired chip sequence or chip of the chip sequence when required.
It is noted that in some applications, the number and size of the sequences can be substantial. For example 512 sequences each of length 512 may be required.
The simplest of conventional methods of chip sequence generation apply either a brute force calculation to generate the entire chip sequence from the known algorithm or a robust storage approach which stores in memory all of the chip sequences of the set of chip sequences that will be required in the application. The brute force calculation can be quite time consuming and processor intensive, whereas the storage in memory of all the chip sequences can be memory intensive. To implement either approach cost effectively in hardware would require a relatively large number of components on an integrated circuit. The current requirements in the use of processing speed and memory limits the rate of chip generation and hence limits the number of potential users who require a chip to be generated at a certain rate.
It would be desirable if there was a method or an apparatus for chip sequence generation that did not suffer the problems of these conventional approaches, and moreover increased the efficiency of chip generation for higher rate chip generation.